Think of this method to design a NOT gate (very simple this one) and an OR gate. To provide a known logic state you just have to add a pull down.
In all other cases you need 0 at the output.
TRANSISTOR GATE TABLES SERIES
If you need A & B equal to 1 to have 1 at the output, it means that you have to place two NMOS in series btw the positive supply rail and the output (this is the only way 1 gets to the output). Using NMOS transistors a 1 means the transistor is like a closed switch. I will just explain the AND gate : the only combination of inputs to have a 1 at the output is two 1. Then you write down the truth table of each gate. Obviously with your formula you know there is an AND gate, an OR gate and a NOT gate. I took this course a while ago so I may be glossing over some details or gotchas, but iirc this is how you go from boolean expressions to gates procedurally. So the corresponding pull-up network is:įor fully NMOS logic, if I remember correctly, you forego the active pull-up network for a passive one, where you have a resistor or depletion-mode NMOS (or a PMOS if using pseudo-nmos) to pull the output high when the pull-down network is not active. Product terms become parallel elements and summation becomes series elements. It is called complimentary logic because of how the pull-up network is formed. So the bottom part of your gate looks like this: You can go straight from the boolean expression to your circuit.įor the pull-down network, the product terms become series elements, and summation manifests as parallel elements. The resulting logic circuit has a pull-up network and a pull-down network. I believe the way it was explained was that first you needed a boolean expression in "sum of products form." In your case, you have $$Y = \overline$$ (The inversion here actually simplifies your actual circuit since the logic is typically inverting, and if you did not have the inversion you would have to add an inversion stage) I am having trouble remembering the exact details from this college course I took a few years ago, but we had a unit about combinational logic and creating custom gates using CMOS. How do go solve these types of problems? And or is there a method for doing this? What I tried doing is making a truth table for the gate level circuit.įrom this truth table we can see that when C is 0 then the circuit behaves as a standard NAND gate, and when its on the circuit is always 0, which you could then easily figure out the transistor level circuit, but looking at the truth table like this seems more like it was just luck and won't really work for more complex circuits.Īnother idea I had was that an AND gate is the same thing as two back to back NAND gates, and from there you could figure it out but that seems to result in overly complex circuits. Now how would I go about converting this to transistor level using NMOS? The solution looks like this
We have the function \$X=((A*B)+C)'\$ and the equivalent gate level circuit looks something like this I have an example here to illustate what I am asking.
TRANSISTOR GATE TABLES TRIAL
Is there a good method to go from circuit at gate level or truth table to transistor level, other than trial and error?
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